RTL

DMA issue and writeback engine

hardMemory and Interface ControllersDMAETA: 28 min

Design the control/datapath split for a DMA engine that issues burst reads, tracks outstanding transactions, and writes results back through a response queue.

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Problem Statement

Design the control/datapath split for a DMA engine that issues burst reads, tracks outstanding transactions, and writes results back through a response queue.

Scoring

Transactions, tracking

What to deliver

  • Compilable RTL / UVM / spec as applicable
  • Brief note on trade-offs and timing or coverage assumptions
  • Waveform or log for at least one passing test