Digital Signal Intuition2 problems
Structured Combinational Datapaths2 problems
Sequential Thinking2 problems
StatusProblemDifficulty
Bit-mask comparator blockDigital Signal Intuition • Bit logic • 12 min
easyBarrel shifter and popcount unitDigital Signal Intuition • Bit ops • 14 min
easyParameterized mux fabricStructured Combinational Datapaths • Datapath • 15 min
easyConfigurable ALU sliceStructured Combinational Datapaths • ALU • 18 min
mediumPulse synchronizer and edge detectorSequential Thinking • Sequential • 14 min
easyProgrammable gray counterSequential Thinking • Counter • 18 min
mediumSequence detector with timeoutControl Logic -> FSM Design • FSM • 18 min
mediumPacket parser controllerControl Logic -> FSM Design • Parser • 20 min
mediumReady-valid skid bufferReady-Valid and Flow Control • Handshake • 16 min
mediumElastic pipeline stageReady-Valid and Flow Control • Pipeline • 18 min
mediumTransfer merge controllerReady-Valid and Flow Control • Flow control • 22 min
hardCircular FIFO with occupancyQueues and FIFOs • FIFO • 20 min
mediumWidth-converting gearbox FIFOQueues and FIFOs • Gearbox • 24 min
hardStreaming reduction pipelinePipelining and Throughput Design • Pipeline • 22 min
mediumTwo-stage integer dividerPipelining and Throughput Design • Timing • 25 min
hardRound-robin request arbiterArbitration and Resource Sharing • Arbiter • 18 min
mediumWeighted shared SRAM schedulerArbitration and Resource Sharing • Scheduler • 24 min
hardAXI-lite register fileMemory and Interface Controllers • AXI-Lite • 20 min
mediumDMA issue and writeback engineMemory and Interface Controllers • DMA • 28 min
hardWaveform bug hunt: lost transferVerification and Debug Reasoning • Waveforms • 16 min
mediumFIFO scoreboard smokeVerification and Debug Reasoning • Scoreboard • 10 min
easyCDC formal sign-offVerification and Debug Reasoning • Formal • 28 min
hardStreaming packet processorSystem-Level RTL Integration • System • 30 min
hardOut-of-order load unitSystem-Level RTL Integration • OOO • 35 min
hardMesh NoC router QoSSystem-Level RTL Integration • NoC • 30 min
hard