RTL

Packet parser controller

mediumControl Logic -> FSM DesignParserETA: 20 min

Design the control FSM for a serial packet parser that recognizes header, length, payload, and checksum phases and flags malformed frames.

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Problem Statement

Design the control FSM for a serial packet parser that recognizes header, length, payload, and checksum phases and flags malformed frames.

Scoring

Protocol states

What to deliver

  • Compilable RTL / UVM / spec as applicable
  • Brief note on trade-offs and timing or coverage assumptions
  • Waveform or log for at least one passing test