RTL

Streaming packet processor

hardSystem-Level RTL IntegrationSystemETA: 30 min

Architect a multi-stage packet processor with parse, classify, modify, and enqueue stages using ready-valid boundaries and localized buffering.

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Problem Statement

Architect a multi-stage packet processor with parse, classify, modify, and enqueue stages using ready-valid boundaries and localized buffering.

Scoring

Composition, flow control

What to deliver

  • Compilable RTL / UVM / spec as applicable
  • Brief note on trade-offs and timing or coverage assumptions
  • Waveform or log for at least one passing test