RTL

Two-stage integer divider

hardPipelining and Throughput DesignTimingETA: 25 min

Design a 2-stage pipelined divider with ready-valid I/O. State the latency, throughput, and how stalls propagate across the stages.

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Problem Statement

Design a 2-stage pipelined divider with ready-valid I/O. State the latency, throughput, and how stalls propagate across the stages.

Scoring

Latency, stalls

What to deliver

  • Compilable RTL / UVM / spec as applicable
  • Brief note on trade-offs and timing or coverage assumptions
  • Waveform or log for at least one passing test